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© All Rights Reserved. ApplyBlast.com
Hewlett Packard Enterprise
This onsite role at Hewlett Packard Enterprise involves defining and architecting high-performance blocks for next-generation networking ASICs. Candidates will perform micro-architecture and RTL logic design to maximize throughput while optimizing power efficiency, collaborating with verification and physical design teams to ensure functional correctness and timing closure. The position requires designing networking ASICs for specific protocols like Ethernet and FCoE.
Headquarters
The Woodlands, Texas, United States
Company Size
10001+ employees
Founded
1939
Discover HPE edge-to-cloud, enterprise compute IT, data, and security solutions. Learn how HPE empowers digital transformation through AI and sustainability.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Hewlett Packard Enterprise.
Hewlett Packard Enterprise didn’t post a salary, so this is our estimate from similar listings.
42% below the average for this role
Hewlett Packard Enterprise Announces $2 Billion Debt Offering
17 hours ago
