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© All Rights Reserved. ApplyBlast.com
PALO IT
This role involves owning the module design from specification through silicon bring-up for next-generation firewall platforms, collaborating with verification and physical-design engineers to meet performance and power goals. The position requires expertise in SystemVerilog RTL design, micro-architecture definition, and debugging across simulation, emulation, and silicon. Candidates will partner with cross-functional teams to drive design fixes and pilot AI-driven flows to reduce schedule risk.
Headquarters
Santa Clara, California, United States
Company Size
10001+ employees
Founded
2005
Palo Alto Networks is a global cybersecurity leader that delivers integrated security platforms to prevent cyberattacks across networks, cloud environments, and endpoints. Its portfolio includes next‑generation firewalls, cloud‑native security (Prisma Cloud), AI‑driven detection and response (Cortex), and Zero Trust networking and secure access solutions for hybrid workforces. The company combines hardware and software with threat intelligence, consulting, managed services, and training to help CISOs, SOCs, cloud architects and network teams automate and scale security operations.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for PALO IT.
18% above the average for this role