ASIC DFT Emulation Technical Lead

The ASIC DFT Emulation Technical Lead drives the DFT emulation strategy for Cisco's Silicon One architecture, architecting emulation environments and leading pre-silicon test plan execution. This role involves validating complex scan, MBIST, and JTAG architectures on platforms like Palladium, Veloce, or Zebu while collaborating with front-end RTL, physical design, and ATPG teams. The position ensures seamless silicon bring-up and optimal test coverage for next-generation hardware platforms.