ASIC DFT Engineer

The ASIC DFT Engineer collaborates with front-end RTL and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. This role involves leading the DFT and quality process through the entire implementation flow and post-silicon validation phases for next-generation networking chips. The position requires expertise in DFT, test, and silicon engineering to support Cisco's core Switching, Routing, and Wireless products.