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© All Rights Reserved. ApplyBlast.com
Ericsson
This role focuses on physical-aware synthesis, floorplan-driven netlist optimization, and STA & QoR closure for high-performance, low power SoC designs. The engineer will actively identify opportunities in RTL and microarchitecture levels to improve design PPA while collaborating with various teams throughout the full design cycle. Key responsibilities include executing synthesis flows, driving QoR closure, and validating power intent implementation.
Ericsson is a Swedish multinational telecommunications company that designs, builds and operates mobile and fixed broadband networks and sells related equipment and services to carriers and enterprises. Its offerings span radio access networks (RAN), 5G core and transport, cloud‑native software, OSS/BSS, managed services, private networks, and IoT solutions, with a strong emphasis on 5G deployment and network automation. Ericsson combines hardware, software and professional services to support large‑scale network rollouts, optimization and operation worldwide. It is a major contributor to telecom standards and R&D, widely chosen for its global scale, patent portfolio and carrier expertise.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Ericsson.
Ericsson didn’t post a salary, so this is our estimate from similar listings.
41% below the average for this role
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