Backend Design Expert - Static Timing Analysis (STA) and Logic Synthesis

Renesas is looking for an experienced Backend Design Expert to lead RTL-to-gate conversion, constraint development, and timing closure for high‑performance, low‑power chips. The role involves executing physical‑aware synthesis flows, managing STA across multi‑mode and multi‑corner scenarios, and developing low‑power implementations using UPF, while collaborating with cross‑functional teams.