CPU Design Intern
SiFive
About this role
An Intern on the Out-of-Order Core/Cache Design team at SiFive develops RTL for RISC-V core series using Chisel. The role involves working on projects like RTL feasibility experiments, power analysis, performance enhancements, and designing logic modules.
Skills
Qualifications
About SiFive
sifive.comAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
Recent company news
TracxnSiFive - 2026 Funding Rounds & List of Investors
1 week ago
Data Center DynamicsRISC-V chipmaker SiFive to integrate Nvidia NVLink Fusion into its future chip designs
Jan 19, 2026
SiliconANGLESiFive introduces new processor core designs for AI devices
Sep 8, 2025
Business WireSiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion
Jan 15, 2026
The RegisterSiFive to fuse RISC-V with Nvidia's NVLink
Jan 15, 2026
About SiFive
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Leadership Team
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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View leadership team, funding history,
and employee contacts for SiFive.
Salary
$65k – $78k
per year