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Altera
The role involves leading validation, characterization, and debugging of DDR5 and LPDDR5 memory interfaces on next‑generation FPGA devices. The engineer will develop system‑level validation environments, execute pre‑ and post‑silicon tests, and collaborate with architecture, silicon, board, firmware, and software teams to ensure high‑quality, reliable memory subsystems.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Altera didn’t post a salary, so this is our estimate from similar listings.
18% below the average for this role
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