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Altera
The role involves developing and executing verification plans for DFT and test logic features on complex SoC and IP designs, creating SystemVerilog/UVM-based test environments, and ensuring high-quality silicon through rigorous verification methodologies. The engineer will collaborate with DFT architects, design and validation teams, and drive root‑cause analysis of simulation failures.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Altera didn’t post a salary, so this is our estimate from similar listings.
28% below the average for this role