Altera
The Senior FPGA IP Design Engineer is responsible for owning the architecture, micro-architecture, and parameterizable RTL design of high-performance soft intellectual property blocks. This role involves developing critical system-level IP cores, such as advanced AMBA AXI Interconnect IP, ensuring their portability, scalability, and timing closure across diverse FPGA architectures. The position requires collaboration with verification and physical design teams to resolve technical challenges and provide technical support to customer-facing teams.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Altera didn’t post a salary, so this is our estimate from similar listings.
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