Design Verification Engineer, Staff
Astera Labs
About this role
Astera Labs is looking for a Staff Design Verification Engineer to join their team, focusing on the functional verification of AI connectivity ASICs supporting various high-speed protocols. The role involves full verification lifecycle responsibilities and collaboration across engineering teams in a fast-growing company dedicated to AI infrastructure connectivity.
Skills
Qualifications
About Astera Labs
asteralabs.comAstera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.
Recent company news
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About Astera Labs
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Leadership Team
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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and employee contacts for Astera Labs.
Salary
$160k – $195k
per year