Design Verification Engineer/Lead
France Cars SAS AAA(26 days ago)
About this role
A Senior Design Verification Engineer/Lead on Altera's FPGA IP team responsible for driving verification quality for FPGA interface IPs. The role focuses on ensuring production-ready, bug-free silicon through deep expertise in advanced DV methodologies, tools, and interconnect/serial protocols such as Ethernet and PCIe, while collaborating across architecture, design, and software teams.
Required Skills
- System Verilog
- UVM
- ABV
- Co-Simulation
- EDA Tools
- C++
- C
- Python
- Shell
- TCL
+10 more
Qualifications
- B.Tech in Electronics Engineering
- M.Tech in Electronics Engineering
About France Cars SAS AAA
bloomberg.comBloomberg is a global leader in financial information and technology, providing data, news, and analytics to financial professionals around the world. The company offers an array of products and services, including the Bloomberg Terminal, which delivers real-time data and insights for trading, investment, and risk management. With a commitment to innovation, Bloomberg combines cutting-edge technology with extensive market expertise to empower financial professionals in making informed decisions.
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