Design Verification Engineer/Lead
Altera
About this role
A Senior Design Verification Engineer/Lead on Altera's FPGA IP team responsible for driving verification quality for FPGA interface IPs. The role focuses on ensuring production-ready, bug-free silicon through deep expertise in advanced DV methodologies, tools, and interconnect/serial protocols such as Ethernet and PCIe, while collaborating across architecture, design, and software teams.
Skills
Qualifications
About Altera
altera.comAltera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Salary
$167k – $225k
per year