Principal Design Verification Engineer
Astera Labs
About this role
Astera Labs is seeking a Principal Design Verification Engineer to develop and implement verification strategies for next-generation AI connectivity ASICs supporting PCIe, CXL, Ethernet, and DDR protocols. The role involves leading the full verification lifecycle, collaborating across teams, and improving verification methodologies.
Skills
Qualifications
About Astera Labs
asteralabs.comAstera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.
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About Astera Labs
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Leadership Team
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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View leadership team, funding history,
and employee contacts for Astera Labs.
Salary
$185k – $230k
per year