Design Verification Intern - Master's Degree
Marvell Technology(1 month ago)
About this role
The digital development team at Marvell is seeking a candidate to design, develop, and maintain high-speed interface PHY IPs. This role involves working on verification plans, writing SystemVerilog testbenches, and collaborating with senior engineers to enhance verification environments and improve efficiency through scripting and automation.
Required Skills
- SystemVerilog
- UVM
- Python
- Perl
- C++
Qualifications
- Master’s or Ph.D. in Computer Engineering
- Electrical Engineering
- Computer Science
About Marvell Technology
marvell.comDesigned for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.
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