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Design Verification Manager – IP Group at Astera Labs - ApplyBlast

Design Verification Manager – IP Group

Astera Labs

7 months ago

4.3 on Glassdoor

Israel

Onsite

Full Time

Senior

0 applicants

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About this role

Astera Labs is expanding its R&D presence in Israel and is seeking a Design Verification Manager to lead a team responsible for verifying complex semiconductor chips that enable AI at scale. The role involves defining verification methodologies, overseeing the development of testbenches, and ensuring high standards of hardware quality for AI infrastructure.

Skills

Qualifications

BS in Electrical EngineeringBS in Computer Engineering

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

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Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.