Altera
We are seeking a highly skilled RTL Design Engineer to drive the architecture, development, and implementation of Soft IP solutions for FPGAs. In this role, you will own the end-to-end FPGA Soft IP development lifecycle, including micro-architecture definition, RTL coding, timing closure, simulation, and physical hardware validation. You will collaborate closely with embedded software, hardware, and systems engineering teams to deliver robust, high-performance FPGA solutions.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Altera didn’t post a salary, so this is our estimate from similar listings.
27% below the average for this role