FPGA SW Validation Engineer

This Senior FPGA Engineer role involves validating compiler optimizations, Partial Reconfiguration flows, and debugging features using Quartus Design Software and Altera FPGA hardware. The candidate will create HDL designs, perform regression testing for Quality of Result, and collaborate with cross-functional teams to enhance validation strategies. Expertise in RTL coding, verification, and hardware debugging is essential for resolving customer issues and assessing performance on targeted devkits.