Functional Verification Engineer

The Functional Verification Engineer develops and executes testbenches to verify the functional correctness of digital designs at block and system levels. They create constrained‑random, directed, and coverage‑driven tests using SystemVerilog and UVM, collaborating with design and architecture teams to identify corner cases and ensure full functional coverage before tape‑out. The role also involves mentoring junior team members and coordinating cross‑functional reviews to align verification goals with design requirements.