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Senior Design Verification Engineer at Hewlett Packard Enterprise - ApplyBlast

Senior Design Verification Engineer

Hewlett Packard Enterprise

3 months ago

4.8 on Glassdoor

Sunnyvale, California, United States

Hybrid

Full Time

Senior

0 applicants

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About this role

The Senior Design Verification Engineer at Hewlett Packard Enterprise will develop and execute verification strategies for complex digital designs, focusing on emulation-based verification to ensure functional correctness and performance before silicon tape-out. The role involves building UVM/SystemVerilog testbenches, running directed and constrained-random tests, and collaborating with design and software teams to drive coverage closure and support early software bring-up.

Responsibilities

Develop and execute verification plans for IP and system designs
Build and maintain UVM/SystemVerilog testbench environments
Set up and run designs on emulation platforms
Debug complex design issues using waveform and emulation tools
Drive coverage closure and generate verification sign‑off reports

Skills

Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer ScienceMaster's degree in Electrical Engineering, Computer Engineering, or related field

About Hewlett Packard Enterprise

hpe.com

Headquarters

The Woodlands, Texas, United States

Company Size

10001+ employees

Founded

1939

View Profile

Discover HPE edge-to-cloud, enterprise compute IT, data, and security solutions. Learn how HPE empowers digital transformation through AI and sustainability.