High-Speed Analog Layout Design Engineer

Celero Communications is seeking a High-Speed Analog Layout Design Engineer to lead the layout design of complex analog and mixed-signal IP blocks for advanced optical communication systems. This hands-on technical role involves collaborating with circuit designers, mentoring junior engineers, and ensuring first-pass silicon success through rigorous verification and physical design integration. The position offers the opportunity to contribute directly to cutting-edge chip development in a fast-paced, high-growth semiconductor startup environment.