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Lead Design Engineer at Cadence - ApplyBlast

Lead Design Engineer

Cadence

3 months ago

4.0 on Glassdoor

Bangalore, India

Onsite

Full Time

Senior

0 applicants

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About this role

The Verification Engineer at Cadence defines and executes verification strategies using methodologies like UVM/SystemVerilog to ensure semiconductor design integrity. The role involves creating robust testbench architectures, performing root-cause analysis on design bugs, and utilizing formal verification tools for bug detection. Candidates will manage coverage metrics, oversee gate-level simulations, and lead cross-functional teams to deliver rigorous functional sign-offs for complex designs.

Responsibilities

Define comprehensive verification strategies using UVM and SystemVerilog
Design scalable and robust testbench architectures with Bus Functional Models
Lead root-cause analysis of complex design bugs and implement fixes
Implement constrained-random stimulus generation to explore design spaces
Monitor functional and code coverage metrics for final sign-off

Skills

Qualifications

B.E. in Electronics or VLSIB.Tech in Electronics or VLSIM.Tech in Electronics or VLSIMaster of Science in Electronics

About Cadence

cadence.com

Headquarters

San Jose, California, United States

Company Size

10001+ employees

Founded

1988

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Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.