Altera
A Performance Power Validation Manager at Altera leads validation and debug efforts to ensure silicon products meet power, performance, and quality targets across pre-silicon through high-volume manufacturing. The role coordinates across design, architecture, and manufacturing teams to align on validation methodologies and measurement correlation. Based in San Jose, CA, the position supports delivery of complex silicon systems and driving continuous improvement in validation processes.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
SoC HW (Digital, Analog or PnP) Validation Engineer
Microsoft
Senior Post-Silicon Validation Engineer
K2 Space
Senior Soc Hw Pnp Functional Validation Engineer United States Oregon Hillsboro
Microsoft
Director, Silicon Validation Engineering
Ambiq
SOC Infrastructure/NoC, Power and Performance Validation Engineer
Qualcomm Incorporated
Senior Dpu Performance Validation Engineer Israel Yokneam
NVIDIA