Physcial Design Engineer III
SiliconExpert(5 days ago)
Mountain View, CaliforniaOnsiteFull TimeSenior$95,900 - $209,000Engineering Services
Apply NowAbout this role
The Physcial Design Engineer III will be responsible for full-chip ASIC implementation, optimization, verification, and routing for complex SoCs at advanced nodes such as 3nm, 5nm, and 7nm. They will work independently on critical design tasks, ensuring successful chip delivery and supporting design automation and flow improvements.
Required Skills
- floor Planning
- Timing Constraints
- Physical Synthesis
- Clock Tree Optimization
- Routing
- Extraction
- Timing Closure
- DFT
- Antenna Fixing
- Signal Integrity
Qualifications
- Bachelor's or Master's in Engineering