Altera
Altera is seeking a Physical Design Engineer to implement advanced custom IP and SoC designs from RTL through GDSII, driving timing closure, power optimization, and design sign‑off for next‑generation FPGA technologies. The role collaborates with architecture, RTL, DFT, verification, and methodology teams to deliver high‑quality silicon.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
6% below the average for this role