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Physical Verification at Astera Labs - ApplyBlast

Physical Verification

Astera Labs

7 months ago

4.3 on Glassdoor

Bengaluru, Karnataka, India

Onsite

Full Time

Senior

0 applicants

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About this role

A Physical Verification Engineer at Astera Labs owns the physical verification signoff for complex SoCs and IP blocks at advanced process nodes. The role involves ensuring design correctness, yield, and tape-out readiness through collaboration with physical design, DFT, and PDK teams.

Skills

Qualifications

Bachelor's or Master's degree in Electronics Engineering, VLSI, or related field7+ years of hands-on physical verification experience in semiconductor / VLSI designDeep expertise in DRC, LVS, ERC, and antenna rule checks in production tape-out environmentsExperience at advanced process nodes (7nm and below); 5nm / 3nm is a strong plusProficiency with Mentor Calibre (primary) and/or Synopsys IC Validator / Cadence PVS

About Astera Labs

asteralabs.com

Headquarters

Santa Clara, California, United States

Company Size

201-500 employees

Founded

2017

View Profile

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.