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Post-Silicon Validation Engineering Intern at Cadence - ApplyBlast

Post-Silicon Validation Engineering Intern

Cadence

1 month ago

4.0 on Glassdoor

San Jose, California, United States

Onsite

Internship

Intern

0 applicants

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About this role

This on-site internship role within the Cadence DDR IP group focuses on validating the system-level and electrical performance of internal silicon test chips. The position involves debugging silicon issues in collaboration with design teams and delivering high-quality characterization reports. The intern will work cross-functionally to ensure product functionality, reliability, and successful deployment.

Responsibilities

Validate system-level and electrical performance of internal silicon test chips
Debug silicon issues in collaboration with analog and digital design teams
Deliver high-quality characterization reports and ensure product reliability

Skills

Qualifications

Bachelor's degree in electrical engineeringMaster's degree in electrical engineering

About Cadence

cadence.com

Headquarters

San Jose, California, United States

Company Size

10001+ employees

Founded

1988

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Cadence is a company specializing in electronic design automation (EDA) software and engineering services for the semiconductor and electronics industries. Their tools enable design and verification of integrated circuits, systems on chips, and electronics systems, streamlining the development process for engineers and designers. With a commitment to innovation and excellence, Cadence empowers companies to enhance product performance and reduce time to market through advanced simulation, verification, and design tools.