Principal Design Engineer

BETA CAE Greece(12 days ago)

Pune, IndiaOnsiteFull TimeSenior$177,361 - $237,982 (estimated)

About this role

This role is for a senior design verification engineer specializing in VLSI, with extensive experience in functional verification, environment development, and UVM/SystemVerilog coding. The candidate will lead verification projects for complex designs, potentially focusing on memory IPs like DDR, HBM, or GDDR.

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Required Skills

UVM
SystemVerilog
Functional Verification
Environment Planning
Test Plan Generation
Verification Environment Development
Memory Verification
VLSI Design
IP Verification

About BETA CAE Greece

beta-cae.com

BETA CAE Systems is a leading provider of advanced simulation software solutions that cater to the needs of engineers and researchers in various fields, including automotive, aerospace, and manufacturing. With a comprehensive suite of tools for computer-aided engineering (CAE), BETA empowers users to effectively perform tasks related to finite element analysis (FEA), computational fluid dynamics (CFD), and process automation. Recently acquired by Cadence, the company continues to innovate in areas such as machine learning and predictive analysis, bolstering its commitment to enhancing product design and simulation accuracy.

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