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Rambus
Rambus is seeking a Principal Engineer to lead Design for Test (DFT) activities for high‑speed mixed‑signal designs, including IP creation, low‑coverage analysis, silicon debug, and flow deployment. The role collaborates closely with cross‑functional teams such as Test Engineering, EDA R&D, and the MIC Design team to deliver high‑quality silicon and improve yield.
Headquarters
San Jose, California, United States
Company Size
501-1000 employees
Founded
1990
Rambus is a semiconductor and IP company that designs high-performance memory interface chips, interface IP (PHYs/SerDes) and hardware security IP. It licenses silicon IP and supplies semiconductor devices and reference designs used by SoC vendors and system manufacturers to accelerate memory, networking and interface functions across data center, AI, cloud, mobile and automotive markets. Rambus focuses on secure, high-bandwidth, low-latency solutions — including DDR/LPDDR/DDR5/DDR6 controllers and PHYs, high-speed SerDes, and root-of-trust/crypto building blocks — and supports customers with integration, verification and ecosystem partnerships.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for Rambus.
Rambus didn’t post a salary, so this is our estimate from similar listings.
10% above the average for this role
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