Principal Physical Design Engineer

Astera Labs(16 hours ago)

San Jose, CAOnsiteFull TimeSenior$207,000 - $230,000Engineering

About this role

Astera Labs is seeking a Principal Physical Design Engineer to oversee the planning, coordination, and execution of ASIC designs for connectivity used in cloud and network infrastructure. The role involves ownership of the entire RTL to GDS process and collaboration with various engineering teams. It is a fully on-site position aimed at experienced professionals in chip design.

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Required Skills

RTL
GDS
Signoff
Timing Closure
Scripting
Power Planning
Serdes
DRC
LVS
STA

Qualifications

BS in Electrical Engineering or Computer Science
≥10 years of experience in PnR and sign-off for complex SoCs

About Astera Labs

asteralabs.com

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.

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