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Altera
The RTL Design Engineer will lead the architecture, development, and implementation of FPGA Soft IP solutions, handling the full lifecycle from micro-architecture definition and RTL coding to timing closure, simulation, and hardware validation. The role involves close collaboration with embedded software, hardware, and systems engineering teams to deliver high‑performance, robust IP.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Altera didn’t post a salary, so this is our estimate from similar listings.
30% below the average for this role