Senior ASIC Design Verification Engineer - Slingshot

The Senior ASIC Design Verification Engineer at HPE is responsible for all phases of pre-silicon design verification, including methodology definition, testbench development, coverage closure, and sign-off reviews. This hybrid role requires expertise in SystemVerilog and UVM methodologies to develop and verify high-speed networking ASICs. The position involves mentoring staff, driving VLSI innovation, and collaborating within a distributed team environment.