Senior Debug Verification Engineer

As a Senior Debug Design Verification Engineer at Altera, you will drive pre-silicon system verification for SoC, FPGA, and full chip designs using UVM methodology. This role involves defining verification strategies, creating comprehensive test plans, and coordinating cross-functional efforts with design, software, and architecture teams to ensure full coverage. You will leverage expertise in design for debug architectures and ARM/RISC debug to identify performance shortfalls and validate system functionality.