Senior Design Lead - Physical Design

This role involves executing Formal Equivalence Verification (FEV) and Static Timing Analysis (STA) signoff for semiconductor chip designs at block and full-chip levels. The incumbent will debug timing issues, develop automated verification workflows using Python, Perl, or Tcl, and collaborate with RTL, Synthesis, and Physical Design teams to ensure timing closure. Responsibilities include implementing Multi-Corner Multi-Mode (MCMM) flows, analyzing signal integrity effects, and generating signoff-ready reports.