Senior Design Verification Engineer

Astera Labs(7 days ago)

VietnamOnsiteFull TimeSenior$167,334 - $225,209 (estimated)Engineering

About this role

Astera Labs provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink with its COSMOS software. The Senior Design Verification Engineer will be part of the engineering organization supporting verification of digital and mixed-signal connectivity IP to ensure product quality and reliability. The role contributes to the development of Astera Labs' AI infrastructure products through collaboration with design and software teams.

View Original Listing

Required Skills

System Verilog
UVM
Testbenches
Verification
Debugging
Coverage Models
Python
Perl
Shell Scripting
Simulation Tools

+5 more

Qualifications

Bachelor's in Electrical Engineering
Bachelor's in Computer Engineering

About Astera Labs

asteralabs.com

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.