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Senior Design Verification Engineer at Altera - ApplyBlast

Senior Design Verification Engineer

Altera

4 months ago

Hillsboro, Oregon

Onsite

Full Time

Senior

0 applicants

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About this role

Altera is seeking a Senior Design Verification Engineer to lead verification strategies for complex FPGA IPs, subsystems, and SoC-level designs. The role involves developing SystemVerilog/UVM environments, driving coverage closure, and collaborating with cross-functional teams to ensure first-pass silicon success. This position offers technical leadership and the opportunity to influence next-generation programmable technology products.

Responsibilities

Define and execute comprehensive verification plans for complex FPGA IPs and subsystems
Develop scalable SystemVerilog and UVM-based verification environments and infrastructure
Create constrained-random and coverage-driven test strategies to validate design functionality
Perform RTL debugging and root-cause analysis of functional failures
Mentor junior engineers and provide technical leadership within the verification team

Skills

Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science10+ years of experience in Design Verification, ASIC, FPGA, or SoC development8+ years of experience with UVM-based verification environments

About Altera

altera.com

Headquarters

San Jose, California, United States

Company Size

1001-5000 employees

Founded

1983

View Profile

Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.