Senior Digital Design Verification Engineer

Renesas is seeking a Senior Digital Design Verification Engineer to join the team developing complex power management SoCs for AI, datacenter, and enterprise computing applications. The role involves independently owning verification of significant blocks and features from planning through closure, combining hands-on UVM development with close collaboration across architecture, design, and firmware teams. This position requires strong expertise in SystemVerilog, UVM, and coverage-driven verification to ensure product quality and performance.