Senior Physical Design and Timing Engineer

A Senior Physical Design and Timing Engineer at NVIDIA drives the physical design and timing of high-frequency, low-power CPUs, GPUs, and SoCs at block, cluster, and full chip levels. The role involves managing frontend and backend implementation from RTL to GDS2, including synthesis, timing constraints, and power convergence. Engineers collaborate cross-functionally to improve convergence flows and apply expertise in physical design optimization, DFT, and EDA tools.