marvellsemiconductor.com
An ASIC Design Engineer on Marvell's Central Engineering team will own the post-RTL design flow for high-speed SerDes IPs ranging from 10Gbps to 224Gbps. The role involves block and chip-level synthesis, timing closure, DFT generation, and ECOs while collaborating across analog and digital design teams.
Headquarters
Santa Clara, California, United States
Company Size
1001-5000 employees
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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marvellsemiconductor.com didn’t post a salary, so this is our estimate from similar listings.