Altera
This role involves the physical design implementation of custom IP and System-on-Chip (SoC) designs, managing the flow from RTL to GDS for manufacturing readiness. Responsibilities include conducting synthesis, place and route, timing analysis, power distribution, and comprehensive verification signoff using industry-standard EDA tools. The position also requires optimizing designs for power, frequency, and area while mentoring junior team members.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Altera didn’t post a salary, so this is our estimate from similar listings.
47% below the average for this role