SiFive
The Senior Physical Design Engineer is responsible for executing and optimizing the RTL-to-GDS implementation flow for high-performance CPU cores at leading-edge process nodes. This role involves taking ownership of block-level implementation, driving PPA closure, and utilizing ML-enhanced methodologies to achieve aggressive performance targets. The position requires close collaboration with cross-functional teams to ensure high-quality technical execution and design sign-off.
Headquarters
Santa Clara, California, United States
Company Size
501-1000 employees
Founded
2015
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
View leadership team, funding history,
and employee contacts for SiFive.
SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion
Jan 15, 2026
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