Senior RTL Design Engineer
Astera Labs
About this role
A Senior RTL Design Engineer at Astera Labs works on RTL for next-generation transceiver IPs (200G–1.6T) and high-speed DSP implementations that support the company’s rack-scale AI connectivity solutions. The role sits within a high-performance design team contributing to silicon-ready, low-power digital designs for advanced process nodes used in scalable connectivity platforms.
Skills
Qualifications
About Astera Labs
asteralabs.comAstera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.
Recent company news
Simply Wall StreetIs It Too Late To Consider Astera Labs (ALAB) After Its Recent Share Price Volatility
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BenzingaWhy Astera Labs Shares Are Surging On Wednesday - Astera Labs (NASDAQ:ALAB)
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GuruFocusAstera Labs Inc (ALAB) Shares Up 7.9% on Mar 11
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About Astera Labs
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Leadership Team
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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View leadership team, funding history,
and employee contacts for Astera Labs.
Salary
$159k – $213k
per year