Senior RTL Design Engineer

Astera Labs(7 days ago)

HybridFull TimeSenior$159,147 - $213,130 (estimated)ASIC/Hardware Engineering

About this role

A Senior RTL Design Engineer at Astera Labs works on RTL for next-generation transceiver IPs (200G–1.6T) and high-speed DSP implementations that support the company’s rack-scale AI connectivity solutions. The role sits within a high-performance design team contributing to silicon-ready, low-power digital designs for advanced process nodes used in scalable connectivity platforms.

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Required Skills

RTL Design
Verilog
SystemVerilog
Synthesis Tools
Linting Tools
Functional Simulation
Gate-Level Simulation
Timing Closure
PPA Optimization
IP Integration

+4 more

Qualifications

BS in Electrical Engineering
MS in Electrical Engineering

About Astera Labs

asteralabs.com

Astera Labs is a semiconductor company that builds purpose‑built connectivity silicon and system solutions for rack‑scale AI and modern data centers. They design high‑speed retimers, PHY/connectivity devices, interposers and companion firmware/software that extend signal reach, improve link reliability, and enable PCIe/CXL and other accelerator interconnects across cables and backplanes. Astera’s products add telemetry, error monitoring and management features to simplify integration for OEMs, cloud providers and hyperscalers. The company focuses on enabling scalable, low‑latency multi‑node AI training and inference systems.