Altera
Altera is seeking a hands-on Senior RTL Design Engineer to lead FPGA design and platform enablement for development kits. This role involves defining architecture, implementing synthesizable RTL, and managing the Quartus Prime flow from synthesis to timing closure. The position requires bringing up boards, validating interfaces, and collaborating with cross-functional teams to debug and resolve system-level issues.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
Altera didn’t post a salary, so this is our estimate from similar listings.
30% below the average for this role