Senior SoC Design Verification Engineer

A Senior System on Chip Design Verification Engineer leads pre-silicon verification for complex ASICs, focusing on Design for Debug architecture and system functional validation. The role involves creating UVM-based test cases and test benches while collaborating with design, software, and architecture teams to ensure full coverage. Engineers must define verification strategies and utilize tooling to identify performance shortfalls across SoC, FPGA, and full chip designs.