Senior Staff Design Verification Engineer – Memory Sub-System (DDR/LPDDR/HBM )

A Verification Engineer at Marvell's Center of Excellence designs, verifies, and delivers IP subsystem building blocks for custom chips targeting hyperscale cloud and AI markets. The role focuses on creating UVM/System Verilog environments and validating high-speed memory interfaces like DDR, LPDDR, and HBM protocols to ensure compliance and performance. Collaboration with design and silicon teams is essential to drive first-pass-right silicon and reduce integration risks.