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© All Rights Reserved. ApplyBlast.com
Altera
Principal Engineer, Design Verification at Altera leads technical verification for next-generation DDR memory subsystem IP within advanced FPGA products. The role involves defining verification architecture, developing scalable UVM/SystemVerilog environments, and collaborating with design teams across the product lifecycle.
Headquarters
San Jose, California, United States
Company Size
1001-5000 employees
Founded
1983
Altera empowers innovators with scalable FPGA and SoC solutions, spanning high-performance to power- and cost-optimized devices. These devices are designed for cloud, network, and edge applications, enabling flexible acceleration and deployment. The company positions itself as a catalyst for innovation, providing adaptable hardware platforms for diverse workloads. Altera’s mission is to accelerate innovators by delivering versatile programmable logic solutions.
86% above the average for this role
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