Senior Staff Design Verification Engineer – Memory Sub-System (LPDDR/DDR/HBM )

A Senior Verification Engineer at Marvell's Center of Excellence designs and validates critical IP subsystems for high-performance data center and AI chips. The role focuses on creating verification environments for memory interfaces like DDR and HBM using System Verilog and UVM, ensuring protocol compliance and silicon readiness. Collaborating closely with design and architecture teams, the engineer drives coverage closure and debugs complex simulation failures.