Senior Staff EDA Tools Hardware Engineer

This role involves developing and integrating iterative timing closure flows for advanced Automated Place and Route (APR) in Electronic Design Automation (EDA) tools to achieve Power, Performance, and Area (PPA) convergence. The position requires driving the utilization of AI agents to improve RTL-to-GDS workflows and leading efforts in Design-Technology Co-Optimization (DTCO) experiments. Additionally, the incumbent will collaborate with the Intel Foundry team to ensure platform entitlements are reflected in product Technical Feature Maps (TFM) and align stakeholders on deterministic PPA measurement methodologies.