Senior Staff Engineer, Design Verification

As a Senior Design Verification Engineer at Marvell, you will lead the verification of complex SoC and IP designs across high-performance computing, networking, and infrastructure domains. You will define verification strategies, develop test plans using UVM methodologies, and drive closure while mentoring junior engineers and influencing architectural decisions. The role involves deep RTL and system-level debugging, formal verification, and cross-functional collaboration to ensure scalability and performance in next-generation AI and data center architectures.