marvellsemiconductor.com
This role involves working within Marvell's Data Center Engineering Business Unit to develop and integrate Design for Test (DFT) architecture and methodologies for complex ASIC/SoC designs. The engineer will collaborate with global teams to enable customer requirements for Custom and Compute businesses, from pre-silicon validation to post-silicon bring-up. Key duties include managing test flows, driving ATPG generation, and ensuring design quality and testability compliance.
Headquarters
Santa Clara, California, United States
Company Size
1001-5000 employees
Headquarters
San Francisco, CA
Company Size
201-500 employees
Founded
2018
Industry
Technology
Glassdoor Rating
4.2 / 5
Sarah Johnson
Chief Executive Officer
Michael Chen
Chief Technology Officer
Emily Williams
VP of Engineering
David Rodriguez
VP of Product
Jessica Thompson
Chief Financial Officer
Andrew Park
VP of Sales
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