Senior Technical Architect - Physical Design

A Senior Static Timing Analysis (STA) Engineer leads signoff verification using industry-standard tools like Synopsys PrimeTime and Cadence Tempus to ensure timing closure at block and full-chip levels. The role involves executing Formal Equivalence Verification (FEV), debugging complex timing issues, and developing automated workflows using Python, Perl, or Tcl to improve efficiency. This position requires deep expertise in STA fundamentals, signal integrity analysis, and low-power design impacts on advanced technology nodes.